There were two components to the simulation. The initial was an intriguing job: to make sure that the design met the timing demands of the DDR3 by considering time and size suit. The second part was to ensure signal integrity; factors to consider for impedance matching would certainly make sure no impedance interruptions would certainly create signal stability problems. While the signal rates were high, they were low enough for loss to be a significant worry, given the trace sizes involved.
One of the DDR3 needs was that the address and control data would exist in a fly-by setting, linking between the controller and all 4 memory ICs. To stick to the timing restriction that required the clock path to be longer compared to the data and DQS lines, one had to include size to the clock. This, certainly, contravened office demands. Along with this, for the very first and second memory IC, earlier along the path, the information occasionally came from a part of the FPGA, that made the information course quite long.
The trace size in between the memories and FPGA ranged 1.5″ to a number of inches in length. The address and control signals took a trip to all four memory parts, while the data were coming from a part of the FPGA that was potentially farther away. It was a challenge to preserve hold-ups to make sure that the write timing in the DDR3 would work.
To make certain timings matched, standard routing was carried out first and afterwards matched the lengths. It was determined which layers would certainly be made use of for every of the signals and teams travelled with each other; for instance, each data lane was placed on the same layer. An initiative was made to minimize the variety of vias and various other functions needed to get to completion path.
The FPGA had some versatility with respect to which pins could be made use of for which objectives. Nonetheless, as speed boosted, it presented restrictions due to the fact that details groups of pins for certain lanes of data were required. The most significant problem came with the address and control lanes, all taking a trip in big groups on the very same layers of the PCB board.
The obstacle came when it was time to match segments. This was tough because of the absence of room. An easy point-to-point suit for the address and control lanes wouldn’t be adequate. Instead, we matched every segment: in between the controller and the initial IC, very first IC to the second IC, and so forth. Luckily, because the ICs were a specific distance apart, it was essentially a point-to-point match, and the trace sizes were similar. The most significant challenge was matching the segment from the FPGA to the first memory IC. The lengthiest path specified how much time the trace should be, and in some cases we should boost the trace by a huge fraction of an inch to suit this. To include so much size, trombones or accordions were needed, which took up space on the board.
The BGA bundles for the HDMI and FPGA controller presented trace breakout problems. In a similar way, the HDMI controller was a very fine-pitch BGA; it didn’t have very many pins, but it was a 0.5 mm pitch BGA, so bursting out in a conventional pattern would be hard. Although the FPGA wasn’t a particularly large or dense part, as a result of the board’s little dimension, traces might only break out on the east and west sides as opposed to the typical north-south-east-west pattern.