The EA Game firm involved Virtual Reality Solutions to produce a prototype of screen connected to the headgear. This safety helmet screen presented a heads-up screen of instrumentation and digital depictions of important information. The helmet was the heart of the Virtual Reality equipments, making it possible for the individuals to make the most of the whole system for incredible video gaming experience.
PCB demands. The headgear display screen supported the PCB in its mechanical housing, and an HDMI cable fed into the video resource. An optical wire attached to the display screen, which brought light to the headset’s LCOS microdisplay. The light illuminated the screen and was predicted into waveguides that offered details to the user’s eyes.
The headset display was just one of the very first reported binocular HMDs in growth making use of a liquid crystal and silicon microdisplay.This innovative technology substantially lowered the expense, volume and weight of standard helmet-mounted screens, changing bulky optics systems with slim, light-weight, see-through diffractive optics. The screen’s physical requirements posed interesting challenges for the PCB.
( 1) The system had to be tiny sufficient to install to the pilot’s safety helmet and enable motion without creating pain.
( 2) To avoid pilot injury, it needed to right away launch all connections to the plane in the event the pilot needed to eject from the aircraft.
( 3) The boards had to be flexible sufficient to twist around the system’s optical components and accommodate adapters at various angles.
( 4) As a result of size restrictions, the design can only burst out traces on the eastern and western sides of the major FPGA element, rather than a north-south-east-west pattern.
Xilinx offered valuable details concerning time of flight inside the plan, as did the IBIS designs of the Micro memory modules. The plan for the memory component was significantly smaller than the Xilinx FPGA, and the Xilinx time of flight info was important. We had the ability to fine-tune out the differences in the memory components after layout was completed.
The design used a Xilinx FPGA and a 64-bit large DDR3 memory bus, where each of four elements had a 16-bit broad data bus. Timing was matching to a few picoseconds on the flight times via the board. Among the a lot more tough parts of the design was that the link between the FPGA and memory required simulation at a very broadband, so the timing restrictions were tight. With such limited margins, it was very important to think about the travel time of trip inside the packages in addition to on the board. For these factors, die-to-die time of trip was picked, instead of simply pin-to-pin time of trip.